Microprocessor and Computer Architecture
Semester II · BCA 152 · 3 credits
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The syllabus asks for
- What a microprocessor is
- A microprocessor system and its buses
- The 8085 at a glance
- The flag register
- Pins and signal groups
- Instruction cycle, machine cycle, T-state
- Interrupts (introduction)
- A first look at the 8086
- Seeing the ideas: real chips, buses, multiplexing, timing and flags
Key points
- A microprocessor is a CPU on a chip; a system joins CPU, memory and I/O with address, data and control buses.
- The 8085 has an accumulator, six general registers (pairs BC, DE, HL; M = byte at HL), PC, SP and five flags S, Z, AC, P, CY.
- AD0–AD7 are multiplexed; ALE and a latch separate the low address byte from the data.
- An instruction cycle consists of machine cycles (opcode fetch plus reads/writes), each of 3–6 T-states.
- Five hardware interrupts with fixed priority and eight software RSTs.
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The syllabus asks for
- Instruction format and addressing modes
- The instruction groups
- Writing a program
- Counters and time-delay routines
- The stack and subroutines
- Interfacing concepts
- Seeing the ideas: opcodes, addressing modes, loops, delays and the stack
Key points
- Instructions are 1–3 bytes; five addressing modes: immediate, register, direct, register-indirect, implied.
- Instruction groups: data transfer, arithmetic, logical/compare/rotate, branching, stack/I/O/machine control.
- Typical programs follow initialise → loop (process, advance pointer, count) → store → HLT; M with HL walks arrays.
- Delay loops use known T-states; one loop gives 14n + 4 T.
- The stack is LIFO in RAM; CALL/RET use it for return addresses.
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The syllabus asks for
- Architecture, organisation and a little history
- The stored-program organisation
- The registers of the basic computer
- The instruction set of the basic computer
- Timing and control
- The instruction cycle
- Seeing the ideas: stored programs, buses, instruction cycle and interrupts
Key points
- Architecture is what the programmer sees; organisation is how it is built. The von Neumann machine stores program and data together; the memory hierarchy exploits locality.
- The basic computer has AR, PC, DR, AC, IR, TR, INPR, OUTR, a 16-bit common bus and a ripple of load/increment/clear controls.
- Instructions are I + 3-bit opcode + 12-bit address; seven memory-reference, twelve register-reference and six I/O instructions.
- The control unit derives timing T0–T15 from a sequence counter and D0–D7 from the opcode.
- Fetch takes T0–T2, indirect addressing adds a read, and each instruction clears SC when done; an interrupt replaces fetch with the three-step interrupt cycle.
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The syllabus asks for
- Micro-operations and control signals
- Hardwired control
- Microprogrammed control
- The microprogrammed control unit
- A microinstruction format (the Mano example)
- Symbolic and binary microprograms
- Design of the control unit
- Control of the AC register and the ALU
- Seeing the ideas: control units, microinstructions and real control words
Key points
- A micro-operation is one register-level action; a microinstruction packs those of one clock period plus the next-address information; a microprogram is the routine for one machine instruction.
- Hardwired control uses gates, is fast and hard to change; microprogrammed control uses a control memory, is flexible and slower.
- The sequencer chooses the next address by increment, jump, conditional jump, opcode mapping, or subroutine return.
- Mano's 20-bit microinstruction has three micro-operation fields, a condition field, a branch field and a 7-bit address.
- FETCH is three microinstructions, and each machine instruction's routine ends by branching back to FETCH.
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The syllabus asks for
- General register organisation
- Stack organisation
- Instruction formats
- Addressing modes
- Data transfer and manipulation
- Program control
- RISC and CISC
- Computer arithmetic
- Seeing the ideas: RISC and CISC chips, stack, addressing, Booth, floating point and division
Key points
- A register-organised CPU selects ALU operands with two multiplexers and a control word SELA/SELB/SELD/OPR.
- A stack gives LIFO storage, supports calls and interrupts, and evaluates postfix expressions.
- Instruction formats range from three-address to zero-address; addressing modes locate operands flexibly.
- Program control uses flags C, S, Z, V; subroutine calls and interrupts save the return state on the stack.
- RISC: simple, fixed-length, load/store, hardwired, pipeline-friendly; CISC: complex, microprogrammed.
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The syllabus asks for
- The I/O interface
- Asynchronous data transfer
- Modes of transfer
- Priority interrupts
- Direct memory access
- I/O processors and communication processors
- Seeing the ideas: interface chips, handshaking, serial frames, priority chain, DMA and bit stuffing
Key points
- An interface adapts the peripheral to the CPU through data, status and control registers; I/O is isolated or memory-mapped.
- Strobe and handshake coordinate data transfer between unsynchronised units; handshake confirms delivery.
- Programmed I/O polls; interrupt-driven I/O signals; DMA moves blocks with one interrupt at the end.
- Priority is resolved by software polling, daisy chain or a priority encoder; the 8259 extends the 8085's interrupt lines.
- IOPs run their own channel programs; communication processors offload character- and bit-oriented protocols.
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The syllabus asks for
- The memory hierarchy
- Primary memory: RAM and ROM
- Secondary memory: the magnetic disk
- Cache memory
- Virtual memory
- Memory management hardware
- Seeing the ideas: memory chips, the hierarchy, cache mapping, paging and replacement
Key points
- The hierarchy trades size, speed and cost; locality makes it work.
- SRAM for cache, DRAM for main memory, ROM family for non-volatile code; the address map and chip-select decode place chips in the address space.
- A disk's access time is dominated by seek and rotation.
- Caches map blocks by direct, fully associative or set-associative rules, replace by LRU/FIFO/random and write by write-through or write-back.
- Virtual memory pages programs on demand; page faults are handled by the OS using FIFO/LRU-like replacement; TLBs speed translation.
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The syllabus asks for
- Parallel processing and Flynn's classification
- Pipelining
- Arithmetic pipeline
- Instruction pipeline
- Pipeline hazards
- Vector processing
- Multiprocessors
- Seeing the ideas: assembly lines, parallel machines, hazards, branch prediction and Amdahl's law
Key points
- Flynn classifies computers by instruction and data streams; modern machines are mostly MIMD with SIMD units.
- A k-stage pipeline gives up to k-fold speed-up, reduced by fill time, unbalanced stages and hazards.
- Arithmetic pipelines segment operations like floating-point add; the four-segment instruction pipeline overlaps FI, DA, FO and EX.
- Structural, data and control hazards are handled by resources, forwarding/interlocks and branch prediction.
- Vector processors apply one operation to arrays, removing loop overhead; matrix multiplication is the model workload.
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TU assessment: 60% final examination set by the university, 40% internal (assignments, lab work, attendance). Confirm the split in your college's notice.